Backed and Led by Stan Shih: A Capacitor-less DRAM Startup Takes On the Big Three's Thirty-Year Order

Silicon Valley, 2012. The memory-design company where Andy Hsu had spent seventeen years was dissolved. Instead of looking for his next job, he started his own company, NEO Semiconductor.

NEO set out to solve a problem the industry had effectively given up on: rebuilding the structure of DRAM (dynamic random-access memory) so it could be stacked upward the way NAND (flash memory) is. That year, 3D NAND was only just getting started. He pursued this long-doubted direction for fourteen years.

DRAM is an industry with extremely high capital barriers, one that swings wildly with the business cycle. After decades of boom-and-bust attrition, only three players are left standing: Samsung, SK Hynix, and Micron. Together, the Big Three control about 90% of the world's DRAM capacity. In fourth place is China's ChangXin Memory Technologies (CXMT), with roughly 7.6% market share in the first quarter of 2026 — but it is constrained by U.S. export controls and has yet to move into high-end HBM.

NEO has only single-digit headcount, yet its ambition is to get the big memory makers to adopt a method peers had judged "impossible to build" — one that multiplies DRAM capacity eightfold in a single step, without building a new fab.

The capacity problem that has stalled DRAM for twelve years

Memory in a computer comes in two kinds, DRAM and NAND, with different functions and characteristics.

DRAM holds "the data currently being computed": it is fast and can be rewritten at any time, but it is wiped the moment the power is cut. NAND — the flash memory used in SSDs and USB drives — handles long-term storage: high capacity, and it keeps data even without power. What AI computation reads and rewrites over and over is mostly DRAM.

As AI takes off, the appetite of data centers and AI chips for memory has surged, and the market's demand for capacity keeps growing.

To increase capacity, both kinds of memory long relied on the same trick: drawing the circuitry finer and packing more cells onto the same chip — known as "process scaling." But a flat surface has limited area, and beyond a point it can no longer be made finer. From the 20nm node in 2014, DRAM scaling slowed sharply and became hard to push further; as of 2026, twelve years on, it has remained stuck at the 10nm class and has not advanced below 10nm, with single-die capacity climbing only from 8Gb to 32Gb.

NAND hit the wall earlier, but it switched to an entirely new method: rather than cramming into one layer, it stacks upward, piling cells layer by layer — known as 3D stacking. NAND is now mass-produced at more than 300 layers, with 500 layers in sight over the next two to three years, and capacity stacked all the way from 128Gb to 1Tb.

What Andy Hsu wanted to do was apply NAND's upward-stacking method to DRAM.

AI computing demand is growing at extreme speed, pushing memory demand to its limits. In the first quarter of 2026, DRAM contract prices rose about 90% in a single quarter; AI data centers are estimated to consume close to 70% of the world's high-end DRAM in 2026. With demand climbing, DRAM's capacity bottleneck has become the most urgent issue for the entire memory industry — and the fix Andy Hsu has spent 14 years developing could be the way to break through it.

His fix is to bypass one of DRAM's most central — and most obstructive — components: the capacitor. The three big makers have all tried in recent years to stack DRAM upward, and all have been blocked by the physical limits the capacitor imposes. Andy Hsu went the other way: he removed the capacitor.

The capacitor-less (floating-body) approach, drawing on NAND