The Stealth Breaker of Moore’s Law: Why TSMC Bet Big on Advanced Packaging

TSMC leads the world in advanced process technologies below 7 nanometers, and one of its key advantages lies in its breakthroughs in advanced packaging. Launched in 2009, this R&D initiative has now reached mass production at scale, becoming a major milestone in the semiconductor industry’s effort to move beyond Moore’s Law. For TSMC, it represents the company’s most strategically critical weapon in overcoming the technological bottlenecks of the post-Moore era.

TSMC traditionally focused on front-end wafer fabrication technologies, while the back-end packaging processes were typically outsourced to specialized providers such as ASE. However, as process technology approached its physical limits, TSMC began investing heavily in packaging and redefined it as “advanced packaging.”

Advanced packaging refers to a new class of technology that goes beyond traditional “single-layer” packaging. As semiconductor manufacturing progresses to 7nm, 5nm, and even 3nm nodes, chip design becomes increasingly complex and costly. To address these challenges, TSMC began exploring vertical chip stacking—through 2.5D or 3D packaging—to build chips upward, much like constructing a high-rise building.

As chips are increasingly stacked vertically, the role of advanced packaging is to integrate multiple small chips to maximize performance. After TSMC successfully developed its advanced packaging technologies, major clients like Apple, AMD, and NVIDIA began adopting chiplet-based heterogeneous architectures for their next-generation designs. TSMC integrates these chiplets into a single system using 2.5D and 3D packaging, driving the mainstream adoption of AI and high-performance computing (HPC) processors.

According to market research firm Yole, the advanced packaging market is projected to grow at a compound annual growth rate (CAGR) of 15% from 2020 to 2026. By 2026, the market is expected to reach $48 billion, surpassing the size of the traditional packaging sector.

TSMC’s entry into advanced packaging technology has a lesser-known origin story. In 2009, Morris Chang returned as CEO of TSMC and invited his former R&D vice president, Jiang Shang-Yi, out of retirement to lead the company’s technology development efforts.

At the time, Jiang Shang-Yi made a bold proposal to Morris Chang: while progress in process technology was slowing and Moore’s Law was nearing its limit, there was still significant room to improve system-level efficiency. He argued that advanced packaging could address the inefficiencies caused by individual chip units operating independently on circuit boards, enabling greater overall performance.

Jiang Shang-Yi laid out in detail the importance of advanced packaging technology and urged greater investment in both talent and resources. After about an hour of discussion, Morris Chang made a swift decision: he allocated 400 R&D personnel and $100 million for equipment purchases, instructing Jiang to immediately launch the development of advanced packaging.

At the time, few outside the company recognized the strategic significance of TSMC’s investment. The advanced packaging department was on the verge of being dismantled, but Jiang Shang-Yi’s return led to the rehiring of key engineers and revitalization of the team. Advanced packaging soon became the primary focus of his second tenure at TSMC.

In the end, TSMC successfully paved the way in advanced packaging, prompting many of its industry peers to follow suit. Today, there is broad consensus that this is the path forward in the post-Moore’s Law era.

TSMC later developed its InFO (Integrated Fan-Out) packaging technology, which enabled it to win iPhone processor orders away from Samsung. It also introduced CoWoS (Chip-on-Wafer-on-Substrate), widely used in NVIDIA’s deep learning chips. These advanced packaging breakthroughs have become key drivers of TSMC’s remarkable growth in recent years.

A single remark from a Qualcomm executive changed everything

During the development of advanced packaging, Jiang Shang-Yi and his longtime collaborator, Yu Zhen-Hua, now a TSMC Distinguished Fellow and Vice President, led a team of hundreds of engineers. In 2012, they launched TSMC’s first-generation packaging technology, CoWoS (Chip-on-Wafer-on-Substrate). However, initial adoption was minimal, with only Xilinx and Huawei’s semiconductor arm, HiSilicon, utilizing the technology.

Although Jiang Shang-Yi actively pitched the technology to clients, most showed little interest. A turning point came when a vice president at Qualcomm told him, “Our expectation for packaging cost is one cent per square millimeter.” Jiang then asked his team to calculate the actual cost of CoWoS, which turned out to be seven cents per square millimeter. That was when he realized that having advanced technology was one thing—but if the cost far exceeds customer expectations, it becomes an entirely different challenge.

As a result, TSMC’s subsequent development of InFO (Integrated Fan-Out) successfully reduced packaging costs to below one cent per square millimeter. The technology attracted a wide range of clients, including Apple, which abandoned its chip orders with Samsung and placed large-volume orders with TSMC instead.

For Jiang Shang-Yi and the TSMC development team, the Qualcomm executive’s remark was a wake-up call. With over four decades of experience in engineering, Jiang had rarely approached problems from the customer’s perspective. But that single comment prompted him and his team to confront the issue of high costs head-on and to consider how this new packaging solution could become viable by aligning with customer cost expectations.

Today, TSMC has unified its advanced packaging technologies under the name “TSMC 3DFabric,” which includes 3DIC platforms such as SoIC (System on Integrated Chips), InFO, and CoWoS. These technologies offer the industry comprehensive and versatile solutions for integrating logic chiplets, high-bandwidth memory, and specialty process chips, enabling the development of increasingly innovative product designs.

Here’s a notable side story: During his tenure as Vice Chairman at China’s SMIC (Semiconductor Manufacturing International Corporation), Jiang Shang-Yi tried to promote advanced packaging and chiplet technologies within the company. Still passionate about these innovations, he held extensive discussions with then-Chairman Zhou Zixue in hopes of realizing his vision at SMIC. Unfortunately, the company showed little interest in his ideas, and Jiang later admitted that joining SMIC was one of the biggest mistakes of his career.

As SMIC (Semiconductor Manufacturing International Corporation) pursued advanced process technologies, its inability to acquire EUV lithography tools posed a major obstacle. Just as critical, however, was its failure to recognize the importance of advanced packaging early on—a misstep that proved to be a serious setback in its technological advancement.

To overcome the limitations of Moore’s Law, TSMC established an internal “Beyond Moore Office.” While continuing to push the limits of process miniaturization, the company has also made aggressive moves into advanced packaging to break through the constraints of traditional IC architectures. This dual-track strategy has significantly widened TSMC’s technological lead over its competitors.

In addition to its technological breakthroughs, TSMC is accelerating the expansion of its advanced packaging capacity. The company’s newest facility, named AP6 (Advanced Packaging Fab 6), located in Zhunan, Miaoli, is 1.3 times the combined capacity of its four previous plants. It began volume production in the third quarter of 2022.

TSMC originally operated four advanced packaging and testing facilities located in Hsinchu, Tainan, Longtan in Taoyuan, and Taichung. However, due to the cultural aversion to the number “4” in Chinese society, the facilities were named Advanced Packaging Fabs 1, 2, 3, and 5.

TSMC’s advanced packaging facility in Zhunan differs from its other plants in terms of production focus. It is primarily dedicated to front-end 3D integration projects under the TSMC-SoIC (System on Integrated Chips) platform, including advanced technologies like Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW). To strengthen technological independence and localize equipment components, TSMC has also actively supported domestic suppliers, promoting the localization of materials, in-house development of technologies, local manufacturing of foreign equipment, and the domestication of advanced packaging tools.

In the field of front-end semiconductor manufacturing equipment, the market has long been dominated by five global giants: Applied Materials, Lam Research, KLA, ASML, and Tokyo Electron (TEL), which together hold over 70% of the market share. In contrast, the back-end packaging equipment sector is less competitive, with lower technical complexity and cost, giving domestic equipment makers more room to enter.

For instance, Wanrun Technology’s dispensers stand out for their strong technical performance, competitive pricing, and reliable lead times, earning them numerous orders. Other key local suppliers include Csun Manufacturing for wet-process equipment, Gudeng Precision for photomask and wafer boxes, and KYEC (Kuang Yung Enterprise Co.) for semiconductor target materials. As TSMC rapidly expands its advanced packaging technologies and capacity, Taiwan’s equipment, materials, and testing sectors are rising alongside it—forming a tightly integrated ecosystem now known as the “TSMC alliance.”